(1) Field of the Invention
This invention relates to testing and diagnostics of line processes used for the manufacture of integrated circuit devices and more particularly to critical dimensional measurement of sub-tenth micron pattern features during wafer processing.
(2) Description of Prior Art
The manufacture of large scale integrated circuits in a mass production facility involves hundreds of discrete processing steps beginning with the introduction of blank semiconductor wafers at one end and recovering the completed chips at the other. The manufacturing process is usually conceived as consisting of the segment wherein the semiconductor devices are formed within the silicon surface (front-end-of-line) and the portion which includes the formation of the various layers of interconnection metallurgy above the silicon surface (back-end-of-line). Most of these processing steps involve depositing layers of material, patterning them by photolithographic techniques, and etching away the unwanted portions. The materials consist primarily of insulators and metal alloys. In some instances the patterned layers serve as temporary protective masks. In others they are the functional components of the integrated circuit chip.
In order to monitor the integrated circuit manufacturing process, test structures, representative of the circuit elements are typically incorporated in regions of the wafer outside the integrated circuit chips. Examples of these in-line test devices are a dumb-bell structure testable with a four point probe to establish proper resistivity of a deposited layer, or long serpentine metal lines which can be tested to establish the presence of particulate defects by testing for electrical opens and shorts. These devices are typically designed with critical areas much larger than their corresponding elements in the integrated circuit so they are more sensitive to defects and can be tested at various stages during processing. In addition to such devices which characterize the cleanliness and integrity of the process line, tests sites must also be provided which can characterize the integrity of the pattern alignment and its planar dimensions. For this it is desirable to have a means of providing features which are not produced by the same process which produces the pattern. In other words, it would be desirable to have structures by which the can provide a dimensional and alignment reference for evaluating the patterning process. Of particular interest in this application is the ability to accurately measure and characterize the planar integrity of polysilicon lines which are patterned in a deposited polysilicon layer by plasma etching. For this purpose CD (critical dimension) control wafers are used. In present technology, the control wafers are prepared with a polysilicon layer into which lines have been patterned using conventional photolithography and etching. The lines are then calibrated by measurement with a laboratory standard scanning electron microscope (SEM). The calibrated CD control wafer is then used to calibrate and monitor the line SEMs which are routinely used for quality control by the integrated circuit manufacturing line. The line SEMs are used to monitor and verify the critical dimensions of features on and product wafers.
Optical photolithography has been the preferred method for patterning features on integrated circuits for many decades. While its limitations have often been wrongly anticipated for years as integrated circuit technology advanced to smaller and smaller dimensions, optical photolithography has nevertheless managed to keep in step and remain the most cost effective and reliable patterning process. At present, device dimensions are at the sub tenth micron level and are expected to continue to shrink in the future. The desired dimensional and alignment reference structures mentioned supra must therefore be formed by a non-photolithographic process.
Unfortunately, polysilicon lines patterned by these conventional photolithographic and etching processes, which are the essentially the same as those used to manufacture the IC product, suffer from a number of problems which compromise their desirability as calibration standards. These problems include edge roughness and poor dimensional uniformity. In addition, because the lines are of polysilicon, they tend to become charged during the SEM measurement resulting in serious image distortion. It would therefore be desirable to have a critical dimension calibration standard for manufacturing SEMs which includes SEM measurable features which have dimensional parameters comparable to the IC product but without the shortcomings of those formed by the manufacturing processes of the IC product. For example the problem of charging during SEM measurement would be greatly reduced if not entirely eliminated if the calibration feature (lines) on the SEM calibration wafer were made of a material more conductive than polysilicon, such as aluminum or gold. Similarly, the problems of edge roughness and uniformity could be overcome on the calibration wafer by forming the line by a process other than photolithography and etching. These problems are addressed and overcome by the teaching of the present invention.
Focused ion beams have been used for years to thin or remove layers using a hardmask or a photoresist mask. An early example of this form of micro machining or milling using a focused ion beam is cited as early as 1976 by Garvin, et. al., U.S. Pat. No. 3,988,564. Progress was relatively slow with regard to patterning with a focused ion beam (FIB) slow because, like electron beam patterning, it took a relatively long time to pattern photoresist on a wafer by scanning a single beam. This became even more impractical as wafer size increased from about 75 mm. to the present day 150 mm. wafer. Furthermore, FIB systems could not bring about high ion currents at small spot size. More recently Leung, et. al., U.S. Pat. No. 5,945,667 cited an improved ion beam system which overcome these problems. Nevertheless, full wafer patterning of today's large wafers with a single FIB is still not practical. However, FIB technology, particularly, now with greatly improved small spot size and high ion currents, is found by the present inventors, to be useful as well as practical for providing independent reliable test structures for critical dimension measurements and SEM calibration in the sub tenth micron process technology.
Russell, et. al., U.S. Pat. No. 6,514,866 B2 shows a method for micro machining a copper film with a focused beam of gallium Ions while the film is in an ambient of organic chloride or organic hydroxide vapor. The gallium ions selectively sputter the copper, producing a rough surface thereon, while neighboring material, such as a dielectric is not removed. In another similar application, Takigawa, U.S. Pat. No. 4,457,803 uses a focused beam of argon ions to selectively sputter an oxide film.
Azuma, et. al., U.S. Pat. No. 5,683,547 shows a method for using a focused energy beam such as an ion beam to assist the local etching of a material with an etchant gas. Satya, et. al., U.S. Pat. No. 6,528,818 shows a method for scanning a region on a wafer for defects using a charged particle beam. Takano, et. al., U.S. Pat. No. 6,538,844 B2 shows a method for fabricating a magnetic head by focused ion beam etching while Talbot, et. al., U.S. Pat. No. 5,616,921 shows a method for controlling preferential etching during focused ion milling by using a mask image.